# Other bistablesElectronics guide > Digital integrated circuits II > Other bistables

There is more than one type of bistable — the SR-type is in reality only the simplest. They all derive from the SR-type bistable however, and so it’s the SR-type bistable that we’ll use as the basic building block when making them.

The clocked SR-type bistable

Figure 11.8 shows the clocked SR-type bistable. It is a simple adaptation of the basic SR-type NAND bistable, in that it features an extra pair of NAND gates, which not only allows inputs which do not require inverting, but also allows a clocked input to be part of the circuit’s controlling mechanism.

Now, a clock circuit can be made from something like a 555 astable multivibrator (as we saw in Chapter 5), and how it is made is unimportant to us here. What is important, on the other hand, is that a clock means that several bistables can be synchronised, all in time with the clock.

Figure 11.8 A clocked SR-type NAND bistable

The clocked SR-type NAND bistable circuit here functions basically as before, except that the outputs can only change states while the clock input CLK is at logic 1. When the clock input CLK is at logic 0, it doesn’t matter what logic levels are applied to the S and R inputs, there will be no effect on the bistable.

Thus, with this simple addition, we have created a bistable with a controlling input. Unless the controlling input is at logic 1, nothing else can happen. This can be a very useful thing in electronics where, say, a number of things need to be counted over a period of time. For example, by clocking the circuit for, say, 1 hour, the number of cars passing a checkpoint in that time could be counted electronically.

The D-type bistable

A variation on the basic clocked SR-type bistable is the ‘data’ bistable, or D-type bistable. A circuit is shown in Figure 11.9.

Figure 11.9 A D-type bistable

Effectively, the output of the first NAND gate (which would be the inverted S input) is used as the input to the second (which would be the R input). The single remaining input is given the label D.

In operation, the Q output of the D-type bistable will always follow the logic level at D while the clock signal CLK is at logic 1. When the clock falls to logic 0, however, the output Q remains at the last state of the D input prior to the clock changing.

This is quite a useful circuit, and is relatively simple in terms of both circuitry and operation. Like the simple SR-type bistable, it can be used to measure input signal variations over a defined period of time.

The edge-triggered SR-type bistable

However, often it’s necessary that things are registered at a precise instant of time, not over a period. So the circuits of Figures 11.8 and 11.9 can’t be used. A moderately simple adaptation to ensure a circuit only registers input changes at an instant is all that’s required — it’s basically a combination of two identical clocked SR-type NAND bistables, each operating on opposite halves of the clock signal — and the resultant circuit is shown in Figure 11.10.

Such a combination of two bistables is often called a ‘master–slave’ bistable, because the input bistable operates as the master section, while the output bistable is slaved to the master during half of each clock cycle.

Figure 11.10 An edge-triggered SR-type NAND bistable

An important component is the the inverter which connects the two bistables in the circuit. This ensures that the bistables are enabled during opposite half cycles of the clock signal.

Assuming that the clock input CLK is at logic 0 initially, the S and R inputs cannot yet affect the master bistable’s operation. However, when the clock input CLK goes to logic 1 the S and R inputs are now able to control the master bistable in the same way they do in Figure 11.8. As the inverter has inverted the clock signal though, the slave bistable’s inputs (which are formed by the outputs of the master bistable) now have no effect on the slave’s outputs. In short, although the outputs of the master bistable may have changed, they do not yet have any effect on the slave bistable.

When the clock input CLK falls back to logic 0 the master bistable once again is no longer controlled by its S and R inputs. At the same time, however, the inverted clock signal now allows the slave bistable’s inputs to control the slave bistable. In other words, the final outputs of the circuits can only change state as the clock signal CLK falls from logic 1 to logic 0. This change of state from logic 1 to logic 0 is commonly called the ‘falling edge’, and the overall circuit is generically known as an ‘edge-triggered’ bistable.

This is an extremely important point in electronic terms. By creating this master–slave bistable arrangement to make the bistable edge-triggered, we are able to control precisely when the bistable changes state. As a benefit, this also makes sure that there is plenty of time for the master and slave bistables comprising the overall bistable to respond to the input signals — although things in logic circuits change and respond quickly, they do not happen instantly and still do take a finite time. The master–slave arrangement takes account of and caters for this small but finite time.

The JK-type bistable

One other problem which we’ve already encountered with our basic bistables isn’t yet catered for though — the indeterminate output which can occur in a bistable if both S and R inputs are logic 1 at the moment when the clock signal falls from logic 1 to logic 0.

So, to prevent this happening, it’s a matter of preventing both S and R inputs from being at logic 1 at the same time as the clock signal falls from logic 1 to logic 0. We do this by adding some feedback from the slave bistable to the master bistable, and creating new inputs (labelled J and K).

The circuit of such a JK-type bistable to perform this function is shown in Figure 11.11.

Figure 11.11 A JK-type bistable

As with the edge-triggered master–slave SR-type bistable, the outputs only change on the falling edge of the clock CLK signal, so the inputs (J and K now, not S and R) control the output states at that time. However, the feedback from the final output stage back to the input stage ensures that one of the two inputs is always disabled — so the master bistable cannot change state back and forth while the clock input is at logic 1. Instead, the enabled input can only change the master bistable state once, after which no further change of states can occur.

Because the JK-type bistable is completely predictable in this manner, under all circuit conditions, the JK-type bistable is the preferred minimum bistable device for logic circuit designers. That’s not to say that SR-type bistables can’t be used, and in fact they do have their purposes, but the important point is that circuit designers have to be aware of their limitations, ensuring that unpredictable outcomes are not allowed and so are designed out of the circuit.

T-type bistable

One particular mode of operation of the JK-type bistable is of importance here. If both J and K inputs are held at logic 1, the outputs of the master bistable will change state with each rising edge of the clock signal and the final outputs will change state for each falling edge. Such a fact is used as the basis of the T-type bistable (where T stands for ‘toggle’), shown in Figure 11.12. The lone T input of this circuit is really just the CLK inputs of other bistables.

Figure 11.12 A T-type bistable

And that concludes our look at how logic bistable circuits are made up from basic logic gates. The important point about all of this though, is that by taking basic combinational logic gates and joining them in what are fairly basic circuits, we have created sequential circuits — that is, logic circuits that have an element of memory!

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